1. Field of Use
The present invention relates to systems for processing requests and more particularly to apparatus for controlling the internal operations of a computer in response to external requests.
2. Prior Art
With the advent of high performance microprocessors, it becomes important to speed up as much as possible memory data transfers to maintain maximum throughput. This is particularly important in the case of modern reduced instruction set (RISC) microprocessors which rely on efficient instruction execution through several pipeline stages. In RISC processors, the only memory operations permitted are loads and stores. The load/store architecture is intended to simplify the design of the processor and allow the program to hide or mask the delay caused by memory accesses.
To reduce memory load delays, certain RISC chips include on-chip instruction and data caches. An example of one such chip is the Intel i860 microprocessor manufactured by Intel Corporation. Another approach has been to rearrange the sequence of instructions so that a useful instruction which does not depend on load data is placed in the time slot following the load instruction (i.e., called the load-delay slot).
While the above approaches reduce internal delays, they are not suitable for reducing overhead normally associated with the handling of external activity. To facilitate such processing, either normally substantial architectural changes must be made to such RISC microprocessors or externally created jump commands without architectural changes must be employed which require substantial time for execution.
Accordingly, it is a primary object of providing a technique for reducing overhead processing in high performance microprocessor chips.
It is a further object of the present invention to provide for reduced overhead without having to change the basic architecture of the high performance microprocessor chip.